A distributed control architecture is a state-of-the-art control architecture for use in an ESS (Electronic Switching System), wherein a number of processors performing a variety of functions are involved and practical and useful cooperations between the processors are achieved by using a so-called IPC (Inter-Processor Communications) network.
For an efficient inter-processor communications system based on the IPC network, there are employed nodes at some intermediate points of the IPC network in order to route and arbitrate a data flow between the processors. To each of the nodes, an independent and unique node address is assigned.
An IPC message format, as shown in FIG. 1, is used for carrying data exchanged between the nodes. The IPC message format comprises sectors such as a SF (start flag), a routing address, IPC data, a CRC (cyclic redundancy check) and an EF (end flag).
The SF and the EF are reserved for indicating the start and the end of the IPC message format, respectively. The routing address is allocated for carrying a node address to which the IPC message format is to be finally delivered. The IPC data refers to the contents of the message that a sending processor wants to deliver to a receiving processor. The CRC represents a sector for carrying CRC data conforming to a well-known CRC test.
Typically, one byte for each of the SF and the EF, and two bytes for each of the routing address and the CRC may be allocated. The size of the IPC data may vary.
A conventional IPC message router is shown in FIG. 2. The conventional router fundamentally compares a node address and a routing address in order to generate a receive enable signal (RXEN), wherein the RXEN is a one bit logic signal determining whether a node accepts or rejects the IPC data incoming therefor. Details on the conventional router will be described by reference to FIG. 2 to FIG. 4.
Referring to FIG. 2, the node address and the routing address are compared in a bit-by-bit fashion within an address comparator 20. The node address is designed to come either from a processor in charge of supervising the IPC or from a wire strap which provides node addresses for the nodes involved in the IPC. The routing address, as stated above, may be extracted from the IPC message. The node address is an address uniquely assigned to each node. The routing address, as stated above, represents a node address to which the IPC message is to be eventually delivered. A mode selector may consist of 3 bits, and is used for determining the comparison pattern performed in the address comparator 20. The address comparator yields logic "0" for the RXEN if the two addresses are matched; logic "1" for the RXEN if the two addresses are not matched.
The comparison is performed by using sixteen XOR (exclusive OR) gates 31 to 32 and an OR gate 33 as illustrated in FIG. 3. Each XOR gate compares each digit of the addresses. The output of the XOR gate is logic "0" when the two inputs are identical and logic "1" otherwise. If all the bits are matched, all the XOR gates produces logic "0". ORing the outputs of the XOR gates yields logic "0" only if all the digits are matched, that is, the RXEN is logic "0". When the RXEN is logic "0", the IPC message is accepted by the node having the node address compared.
The above mentioned comparison should be performed for every node involved.
In order for the conventional router to support the so-called "multi-cast routing", casting the IPC message to more than one node at the same time, the conventional router ought to be equipped with exceedingly complicated logic devices. This can be a significant drawback.
Further, if yielding the RXEN is not completed within one period of a CLK (system clock), e.g., the interval between t1 and t2 shown in FIG. 4, the IPC message itself must be delayed. More specifically, a delay from time t1 when the comparison is initiated as shown in FIG. 4 is extended over time t2, a stream of IPC messages must be delayed by one or more clocks so as not to cause loss in the IPC messages. Dealing with the delay of IPC messages, however, exacts additional resources and extra cost.